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53TCP2EndianRegister(TCPEND).......................................................................................44
54TCP2ErrorRegister(TCPERR)..........................................................................................45
55TCP2StatusRegister(TCPSTAT).......................................................................................47
56TCP2EmulationRegister(TCPEMU)...................................................................................49
57DataSource-EDMA3(BigEndian).....................................................................................50
58DataDestination-Kernel(LittleEndian)................................................................................50
59DataSource-Kernel(LittleEndian).....................................................................................50
60DataDestination-EDMA3(BigEndian)................................................................................50
61DataMemory................................................................................................................51
62EN=1(Little-EndianMode)Rate=1/2.................................................................................51
63EN=0(Big-EndianMode)Rate=1/2...................................................................................51
64EN=1(Little-EndianMode)Rate=1/3.................................................................................51
65EN=0(Big-EndianMode)Rate=1/3...................................................................................51
66EN=1(Little-EndianMode)Rate=1/4.................................................................................51
67EN=0(Big-EndianMode)Rate=1/4...................................................................................52
68EN=1(Little-EndianMode)Rate=1/5.................................................................................52
69EN=0(Big-EndianMode)Rate=1/5...................................................................................52
70EN=1(Little-EndianMode)Rate=3/4.................................................................................52
71EN=0(Big-EndianMode)Rate=3/4...................................................................................53
72SourceofEndiannessManager-OrderingofHardDecisionsin32-BitWord(OUT_ORDER=0)............53
73DestinationofEndiannessManager-OrderingofHardDecisionsin32-BitWord(OUT_ORDER=0).......53
74SourceofEndiannessManager-OrderingofHardDecisionsin32-BitWord(OUT_ORDER=1)............53
75DestinationofEndiannessManager-OrderingofHardDecisionsin32-BitWord(OUT_ORDER=1).......53
76SourceofEndiannessManager-TrellisStageOrderingofHardDecisionsin32-BitWord(OUT_ORDER
=0)...........................................................................................................................53
77DestinationofEndiannessManager(OUT_ORDER=0).............................................................54
78TrellisStageOrderingofHardDecisionsin32-BitWord(OUT_ORDER=1).....................................54
79TrellisStageOrderingofHardDecisionsin32-BitWord(OUT_ORDER=1).....................................54
80DataSource=Kernel......................................................................................................54
81DataDestination=EDMA3EN=0(Big-EndianMode)...............................................................54
82TCP_ENDIANRegister....................................................................................................55
83InterleaverIndexesinDSPMemory(ENDIAN_INTR=1)............................................................56
84DataSource-EDMA3(ENDIAN_INTR=1)............................................................................56
85DataDestination-Kernel(ENDIAN_INTR=1)........................................................................56
86InterleaverIndexesinDSPMemory(ENDIAN_INTR=0)............................................................56
87DataSource-EDMA3(ENDIAN_INTR=0)............................................................................57
88DataDestination-Kernel(ENDIAN_INTR=0)........................................................................57
89ExtrinsicinDSPMemory(ENDIAN_EXTR=1)........................................................................57
90DataSource-Kernel(ENDIAN_EXTR=1)............................................................................58
91DataDestination-EDMA3(ENDIAN_EXTR=1)......................................................................58
92ExtrinsicinDSPMemory(ENDIAN_EXTR=0)........................................................................59
93DataSource-Kernel(ENDIAN_EXTR=0)............................................................................59
94DataDestination-EDMA3(ENDIAN_EXTR=0)......................................................................59
95MAPUnitBlockDiagram..................................................................................................60
96SlidingWindowsandSub-blocksSegmentation(Examplewith5Sub-blocks,framelength≤20730).........61
97SharedProcessingSubframeSegmentation(Examplewith5Subframes)........................................62
98ExampleRFormula........................................................................................................63
99EDMA3ParametersStructure............................................................................................65
100TCP2EventsGenerationinStandalone(SA)Mode...................................................................74
101TCP2EventsGenerationinShared-Processing(SP)Mode.........................................................75
6ListofFiguresSPRUGK1–March2009
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