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7.1.4ExtrinsicData
7.1.4.1ENDIAN_EXTR=1
XT0
XT1
XT2
XT3
XT4
XT6
XT7
XT5
Base 0
Base 7
Endian_Extr=1
XT7
XT6
XT5
XT4
XT0
XT2
XT3
XT1
Endianness
manager
XT7
XT6
XT5
XT4
XT3
XT2
XT1
XT0
63 0 63 0
EDMA3
TCP
Kernel
Memory
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Endianness
Figure87.DataSource-EDMA3(ENDIAN_INTR=0)
634847323116151
INTER1INTER0INTER3INTER2
Figure88.DataDestination-Kernel(ENDIAN_INTR=0)
634847323116151
INTER3INTER2INTER1INTER0
Table37.ExtrinsicData
Little_big_endianENDIAN_INTRDescription(MSBtoLSB)
003,2,1,0,7,6,5,4⇒7,6,5,4,3,2,1,0(bytes)
010,1,2,3,4,5,6,7⇒7,6,5,4,3,2,1,0(bytes)
10Endiannessmanagerhasnoeffect
7,6,5,4,3,2,1,0⇒7,6,5,4,3,2,1,0(bytes)
11Endiannessmanagerhasnoeffect
7,6,5,4,3,2,1,0⇒7,6,5,4,3,2,1,0(bytes)
IfENDIAN_EXTR=1,dataaresavedintheirnativeformat(8bits)intheDSP(seeTable38).
Table38.ExtrinsicinDSPMemory(ENDIAN_EXTR=
1)
Address(hexbytes)Data
BaseEXT0
Base+1EXT1
Base+2EXT2
Base+3EXT3
Base+4EXT4
Base+5EXT5
Base+6EXT6
Base+7EXT7
Figure89.ExtrinsicinDSPMemory(ENDIAN_EXTR=1)
TheyhavetobeswappedasdescribedinFigure90andFigure91.
SPRUGK1–March2009TMS320C6457Turbo-DecoderCoprocessor257
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