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7.1.2TCP_ENDIANRegisterforEndiannessManager
Endianness
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Figure77.DestinationofEndiannessManager(OUT_ORDER=0)
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StageStageStageStageStageStage
N-32N-33N-63NN-30N-31
4.OUT_ORDER=1EN=1(Little-EndianMode)
Figure78.TrellisStageOrderingofHardDecisionsin32-BitWord(OUT_ORDER=1)
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StageStageStageStageStageStage
NN-1N-31N-32N-62N-63
Figure79.TrellisStageOrderingofHardDecisionsin32-BitWord(OUT_ORDER=1)
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StageStageStageStageStageStage
N-63N-62N-32N-31N-1N
Harddecisionsarepackedina32bitwordinsidetheTCP2.Datawillbesavedinwordformat(32bits)in
theDSP.
Table32.HardDecisionsinDSPMemory
Address(hexbytes)Data
BaseHD0(32harddecisions)
Base+4HD1(32harddecisions)
TheyhavetobeswappedasdescribedinFigure80andFigure81.
Figure80.DataSource=Kernel
15870
HD1HD0
R/WR/W
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Figure81.DataDestination=EDMA3EN=0(Big-EndianMode)
15870
HD0HD1
R/WR/W
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
TCP2input/outputdataareofdifferentwidthsandstorageintheDSPmemorysubsystemwillbedifferent
whethertheyaresavedinnativeorwordformat.However,EDMA3willalwaysreadandwritewords.
Thereisaneedtodefineawayofhandlingthedatadependingonwhethertheyaresavedinnativeor
wordsformat.Table33summarizesthedifferentdataformats,aswellasthememory-mappedregister
TCP_ENDIANprogramming(seeFigure82).
54TMS320C6457Turbo-DecoderCoprocessor2SPRUGK1–March2009
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