Filter
Top Products
6.26TCP2EmulationRegister(TCPEMU)
www.ti.com
Registers
Inemulationmode,theaccesstoTCP2memoriescanbedoneinreadorwrite.TCP2supportsemulation
mode.Emulationsupporthelpsinsystemdebug.Emulationmodesareachievedwiththeprogrammable
SOFTandFREEbitsintheTCP2EmulationRegister(TCPEMU)attheconfigurationbusaddress
0x00070.TheTCP2emulationregister(TCPEMU)isshowninFigure56anddescribedinTable31.
Figure56.TCP2EmulationRegister(TCPEMU)
3116
Reserved
R/W-0
15210
ReservedSOFTFREE
R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table31.TCP2EmulationRegister(TCPEMU)FieldDescriptions
BitFieldValueDescription
31-2Reserved0Reserved.Thereservedbitlocationisalwaysreadas0.Avaluewrittentothisfieldhasnoeffect.
1SOFTSOFTbit
0EmulationhaltateitherendofMAPdecodeoratendofdecodepriortolastXEVT.Stopattheend
ofMAPdecodehaspriority.
1EmulationhaltatendofdecodepriortolastXEVT
0FREEFREEbit
0Softemulationbittakeseffect
1TCP2ignoresemulationhaltandrunstocompletion
TheFREEandSOFTbitsaredesignedtoenableaflexiblemethodofhowtheTCP2isoperatedduring
anemulationhaltoftheCPU.TheFREEbitdeterminesifanemulationhaltoftheCPUwillhalttheTCP2
atall.IftheFREEbitisset,andanemulationhaltoftheCPUoccurs,theTCP2willcontinueprocessing
normally.IftheFREEbitiscleared,andanemulationhaltoftheCPUoccurs,thenTCP2willbehaltedin
amannerdeterminedbytheSOFTbitssetting.NotethatwhenFREE=1,SOFThasnoeffect.
GiventhatFREE=0,andanemulationhaltoftheCPUoccurs,theTCP2willhaltasfollowsbasedonthe
settingofSOFTbit.
SOFT=0:
EmulationhaltusesTCP2debugmode.AnycurrentMAPprocessingmustcompletebeforeenteringthe
emulationmode.
Currentdatatransferonthebusshouldcompleteandpendingread/writerequeststo/fromCPU/DMA
shouldcompletebeforeemulationhalt.Ifanactiveoutputevent(TCPREVT/TCPXEVT)isoutputbefore
thisemulationhalt,itshouldservicethatrequestbeforegoingintoasuspendstate.IfanactiveMAPis
processingbeforethisemulationhalt,TCP2shouldservicethatrequestbeforegoingintoasuspendstate.
TCP2willpauseaftereachMAPprocessing.Nonewread/writeeventstoCPUorDMAshouldbe
generated.AnyongoingCPUorDMAread/writeservicestoTCP2shouldcomplete.TheTCP2willrestart
fromthehaltstateanditwillruntonormalcompletionuntilnextemulationhalt.
SOFT=1:
Currentdatatransferonthebusshouldcompleteandpendingread/writerequeststo/fromCPU/DMA
shouldcompletebeforeemulationhalt.Ifanactiveframeisprocessingbeforethisemulationhalt,itshould
serviceallrequestsbeforegoingintosuspendstate.AnyongoingCPUorDMAread/writeservicesto
TCP2shouldcomplete.Frameprocessingshouldcomplete.
SPRUGK1–March2009TMS320C6457Turbo-DecoderCoprocessor249
SubmitDocumentationFeedback