24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
8
3.3 AGP Signals
In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU”
indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor.
Pin name and description IO cell
type
Power
plane
AGP 3.0
Signaling
AGP 2.0
Signaling
During
reset
After
reset
During
reset
After
reset
A_ADSTB0_[P, N].
AGP differential strobe for A_AD[15:0] and
A_CBE_L[1:0]. When AGP 3.0 signaling is enabled,
A_ADSTB0_P is the first strobe and A_ADSTB0_N is the second
strobe.
IO VDD15 Term Term _P: PU
_N: PD
_P: PU
_N: PD
A_ADSTB1_[P, N]. AGP differential strobe for AD[31:16],
A_CBE_L[3:2], and A_DBI[H,L]. When AGP 3.0 signaling is
enabled, A_ADSTB1_P is the first strobe and A_ADSTB1_N is
the second strobe.
IO VDD15 Term Term _P: PU
_N: PD
_P: PU
_N: PD
A_AD[31:0]. AGP address-data bus. IO VDD15 Term Term PU Low
A_CBE_L[3:0]. AGP command-byte enable bus. IO VDD15 Term Term PU Low
A_CAL[D, S] and A_CAL[D, S]#. Compensation pins for
matching impedance of system board AGP traces. See
DevA:0x[54, 50] for more information. These are designed to be
connected through resistors as follows:
Signal
Compensation Function External Connection
A_CALD Rising edge of data signals Resistor to VSS
A_CALD# Falling edge of data signals Resistor to VDD15
A_CALS Rising edge of strobe signals Resistor to VSS
A_CALS# Falling edge of strobe signals Resistor to VDD15
These resistors are used by the compensation circuit. The output of
this circuit is combined with DevA:0x[54, 50] to determine com-
pensation values that are passed to the link PHYs.
Analog VDD15
A_DBI[H, L]. Data bus inversion [high, low]. When
DevA:0xA4[AGP3MD]=1, A_DBIL applies to AD[15:0];
A_DBIH applies to AD[31:16]. 1=AD signals are inverted.
0=A_AD signals are not inverted. The IC uses these signals in
determining the polarity of the A_AD signals when they are
inputs. These may also be enabled to support the DBI function of
the IC output signals by DevA:0x40[DBIEN]. Both A_DBIH and
A_DBIL are strobed with A_ADSTB1_[P, N].
When DevA:0xA4[AGP3MD]=0: A_DBIL is pulled low with the
AGP termination value and not used by the IC; A_DBIH is pulled
up to VDD15 through a weak resistor and becomes the AGP 2.0
PIPE# input signal.
IO VDD15 Term Term PU PU
A_DEVSEL#. AGP device select. IO VDD15 Term Term PU PU
A_FRAME#. AGP frame signal. IO VDD15 Term Term PU PU
A_GC8XDET#. 0=Specifies that the graphics device supports
AGP 3.0 signaling. The state of this signal is latched on the rising
edge of A_RESET# before being passed to internal logic.
Input
w/PU
VDD15 PU PU PU PU
