24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
30
5.3 AGP Bridge Configuration Registers
These registers are located in PCI configuration space, in the second device (device B), function 0. See section
5.1.2 for a description of the register naming convention.
AGP Bridge Vendor And Device ID Register DevB:0x00
Default: 7455 1022h Attribute: See below.
AGP Bridge Status And Command Register DevB:0x04
Default: 0220 0000h Attribute: See below.
AGP Bridge Revision and Class Code Register DevB:0x08
Default: 0604 00??h Attribute: Read only.
AGP Bridge BIST-Header-Latency-Cache Register DevB:0x0C
Default: 0001 0000h Attribute: See below.
Bits Description
31:16 AGP bridge device ID. Bits[31:20] are read only; bits[19:16] are write-once. When the LSBs are left
at the default value, some operating systems may load a generic graphics driver. System BIOS should
program the LSBs to 6h in order to circumvent the loading of such a driver.
15:0 Vendor ID. Read only.
Bits Description
31:9 Read only. These bits are fixed in their default state.
8 SERREN: SERR# enable. Read-write. This bit controls no hardware.
7:3 Special cycle enable. Read only. This bit is hardwired low.
2 MASEN: PCI master enable. Read-write. 1=Enables the AGP bus master to initiate PCI cycles to
the host.
1 MEMEN: memory enable. Read-write. 1=Enables access to the AGP bus memory space.
0 IOEN: IO enable. Read-write. 1=Enables access to the AGP bus IO space.
Bits Description
31:8 CLASSCODE.
7:0 REVISION.
Bits Description
31:24 BIST. Read only. These bits fixed at their default values.
23:16 HEADER. Read only. These bits fixed at their default values.
