YMF724F
September 21, 1998
-47-
CBCLK
CSYNC
CSDI
CSDO
0.8 V
1.5 V
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
1.5 V
2.0 V
t
CBIHIGH
t
CVAL
t
CBILOW
t
CBICYC
t
CVAL
t
COH
t
CSYCYC
t
CSYHIGH
t
COH
t
CSYLOW
t
CISU
t
CIH
Fig.6: AC-link timing
4-6 AC3F2 Interface (Fig.7, 8)
Item Symbol Condition Min. Typ. Max. Unit
ASCLK Cycle Time t
ASCCYC
- 325 - ns
ASCLK High Time t
ASCHIGH
140 - 180 ns
ASCLK Low Time t
ASCLOW
140 - 180 ns
ASCLK to Signal Valid Delay t
ACVAL
*14 - - 50 ns
Output Hold Time for ASCLK t
ACOH
*14 -10 - - ns
Input Setup Time to ASCLK t
ACISU
*15 20 - - ns
Input Hold Time for ASCLK t
ACIH
*15 10 - - ns
ABCLK Cycle Time t
ABICYC
- 325 - ns
ABCLK High Time t
ABIHIGH
140 - 180 ns
ABCLK Low Time t
ABILOW
140 - 180 ns
ABCLK to Signal Valid Delay t
ASVAL
*16 - - 50 ns
Output Hold Time for ABCLK t
ASOH
*16 -10 - - ns
Input Setup Time to ABCLK t
ASISU
*17 20 - - ns
Input Hold Time for ABCLK t
ASIH
*17 10 - - ns
Note) Top = 0-70°C, PVDD=5.0
±
0.25 V, VDD5=5.0
±
0.25 V, VDD3=3.3
±
0.3 V, LVDD=3.3
±
0.3 V, C
L
=50 pF
*14: This characteristic is applicable to ACS and ACDO signal.
*15:This characteristic is applicable to ACDI signal.
*16: This characteristic is applicable to ASDO and ALRCK signal.
*17: This characteristic is applicable to ASDI signal.
