TMP92CZ26A
92CZ26A-435
Stage change condition of control write (no data stage) transfer type
1. Receive SETUP token from host
• Start setup stage in UDC.
• Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
• Change data stage in UDC.
2. Receive IN token from host
• CPU receive request from request register every INT_SETUP
interrupt.
• Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
• CPU process receiving data by device request.
• When CPU finish transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in UDC.
• Return data packet of 0 data to IN token, and state change to IDLE in
UDC.
• Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.
These change condition is
Figure 3.16.12.
Figure 3.16.12 The Control Flow in UDC (Control Write Transfer Type not Dataphase)
SETUP DATA0 ACK IN NAK DATA1
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType registe
bRequest register
wValue register
wINdex register
wLength register
Setup Received registe
EOP registe
IN ACK
